Squatter's Rights: x86 Rounding in Borrowed Bits

Until recently, page after page of Intel’s Software Developer’s Manual documented an instruction called VFMADDRND231PD. It is a fused multiply-add whose rounding direction is set by an immediate byte in the instruction itself. As purplesyringa found, it does not exist. GNU as rejects it, and neither Clang nor ICC has an intrinsic for it. If you hand-encode it from the manual’s opcode line and run it on a Haswell, you get #UD. It is in the 2024 SDM and gone from the 2026 edition, and the most likely story is that it was an early AVX10 prototype someone forgot to delete. That makes it a good place to start a genealogy, because the whole history of rounding control on x86 is a hunt for spare bits. This ghost is the only time Intel tried to give rounding a field of its own, and it never shipped.

The line runs like this. In 1980 the 8087 kept the rounding direction in two bits of the x87 control word. That was global state, changed with FLDCW, and Intel’s optimization manual still warns that cycling it among more than two values costs “delays that are on the order of the pipeline depth.” SSE in 1999 copied the design into MXCSR, where “a write to the register is a serializing instruction” (Agner Fog’s tables put LDMXCSR at about 100 cycles on Pentium 4). In 2007 SSE4.1’s ROUNDPS borrowed imm8 bits for the first per-instruction rounding mode, but only for rounding to an integer. In 2013 AVX-512 finally brought static rounding to real arithmetic by taking over the vector-length field. The SDM §2.7 says that setting EVEX.b on a register-register op will “redirect L’L field (P[22:21]) as static rounding control.” The length then becomes implied (512-bit or scalar), exceptions are forced off, and on memory forms the same bit already means embedded broadcast. One bit carries three meanings. Then Intel’s 512-less E-cores created a problem. The AVX10 whitepaper, Rev 1.0 (2023) promised 256-bit embedded rounding, and the ghost fits that window: a VEX form with a whole byte for rounding, DAZ, FTZ and exception suppression. On paper it was the cleanest rounding control x86 ever had. What reached the spec instead was one more loan. AVX10.2 Rev 1.0 (July 2024), §3.1.3, repurposes EVEX.U, the prefix’s last must-be-one bit. By 2025 that was gone too. Whitepaper Rev 3.0 removed the 256-bit rounding forms, and a run of GCC reverts gave the rationale that it was no longer needed “as somehow a workaround.”

Other branches of the family tree look very different. DEC’s Alpha (1992) wrote rounding qualifiers into the function code of every IEEE operate instruction. Itanium, Intel’s own design from the same years it was rationing x86 prefix bits, gave every arithmetic op an .sf completer that selects among four status fields. RISC-V reserves a 3-bit rm field in every FP instruction and notes that dynamic-mode writes “will serialize the pipeline.” In PTX, fma has no default, so every instruction must spell out .rn/.rz/.rm/.rp. The standard sides with these designs. IEEE 754-2008 §4.2 says statically specified rounding attributes shall be supported, while dynamic modes are only a should, mainly “to support debugging.” For 46 years x86 has supported the optional mechanism natively and put the required one in borrowed bits.

Read as a genealogy, the ghost instruction shows where x86 rounding is going to stay. Every step reused a field that already had a meaning: imm8 bits on one op, then vector length, then a must-be-one bit. Every loan also carried a restriction from the field it borrowed: one operation only, then register-only 512-bit forms, then forced exception suppression. The one design that gave rounding its own byte was retired before it reached silicon. So on x86, the cost of interval arithmetic, double-double libraries and correctly rounded math will keep depending on an encoding accident rather than on the arithmetic. My bet is that no x86 CPU in the APX/AVX10 generation will ship static rounding on memory-operand arithmetic, because EVEX.b on a memory operand already means broadcast and there is no fourth meaning left to hand it. If you are writing a directed-rounding kernel for x86, plan on zmm register-register forms or an MXCSR write. Don’t count on a third option.